About Me

Hi, this is Kangwei Xu. I am now pursuing my Ph.D. degree at the Chair of Electronic Design Automation (EDA), Technical University of Munich (TUM), Munich, Germany, under the supervision of Prof. Ulf Schlichtmann, with guidance from Prof. Bing Li and Prof. Grace Li Zhang. My research focuses on AI for EDA, high-level synthesis (HLS), hardware design, and verification. I have published several first-author peer-reviewed papers in major conferences and journals including DAC, ICCAD, TODAES, JETC, ASP-DAC, MLCAD, etc. I currently serve as a peer reviewer for journals including IEEE Transactions on Computers (TC), ACM Transactions on Design Automation of Electronic Systems (TODAES), Integration VLSI Journal, etc.

Research Interests

• AI for Electronic Design Automation (AI for EDA) Hardware Design and Verification
• LLM-Assisted High-Level Synthesis (C/C++/SystemC to RTL)
• Software-Hardware Co-Design Hardware Acceleration

Publications

1. Kangwei Xu, Bing Li, Ulf Schlichtmann, “LLM for EDA in Front-End Design: Challenges and Opportunities,” ACM/IEEE Design Automation Conference (DAC), 2026.
   Invited Paper in DAC Special Research Session.
2. Kangwei Xu, Bing Li, Grace Li Zhang, Ulf Schlichtmann, “HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2025.
3. Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li, “HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2025.
4. Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li, “CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference,” arXiv preprint: 2511.16395, 2025.
5. Kangwei Xu, Denis Schwachhofer, Jason Blocklove, Ilia Polian, Peter Domanski, Dirk Pflüger, Siddharth Garg, Ramesh Karri, Ozgur Sinanoglu, Johann Knechtel, Zhuorui Zhao, Ulf Schlichtmann, Bing Li, “Large Language Models (LLMs) for Electronic Design Automation (EDA),” IEEE International System-on-Chip Conference (SOCC), 2025.
6. Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li, “Logic Design of Neural Networks for High Throughput and Low-Power Applications,” ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2024.
7. Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li, “HLSRepair: Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models,” ACM/IEEE International Symposium on Machine Learning for Computer-Aided Design (MLCAD), 2024.
8. Kangwei Xu, Ruidi Qiu, Zhuorui Zhao, Grace Li Zhang, Ulf Schlichtmann, Bing Li, “LLM-Aided Efficient Hardware Design Automation,” arXiv preprint arXiv:2410.18582.
9. Kangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard, “An Area-Efficient and Reliable PUF Design with Signature Improvement for STT-mCell Based All-Spin Circuits,” ACM Journal on Emerging Technologies in Computing Systems (JETC), 2022.
10. Kangwei Xu, Yuanqing Cheng, “Fault Testing and Diagnosis Techniques for CNT-Based FPGAs,” ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2022.
11. S. Lu, Kangwei Xu, P. Xie, R. Wang, Y. Cheng, “Testing and Fault Tolerance Techniques for CNT-based FPGAs,” Elsevier Integration, the VLSI Journal, 2025.
12. R. Chen, L. Chen, J. Liang, Y. Cheng, S. Elloumi, J. Lee, Kangwei Xu, V. P. Georgiev, K. Ni, P. Debacker, A. Asenov, A. Todri-Sanial, “Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2022.
13. R. Chen, L. Chen, J. Liang, Y. Cheng, S. Elloumi, J. Lee, Kangwei Xu, V. P. Georgiev, K. Ni, P. Debacker, A. Asenov, A. Todri-Sanial, “Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2022.
14. C. K. Jha, M. Hassan, K. Qayyum, S. Ahmadi-Pour, Kangwei Xu, R. Qiu, J. Blocklove, L. Collini, A. Nakkab, U. Schlichtmann, G. L. Zhang, R. Karri, B. Li, S. Garg, R. Drechsler, “Large Language Models (LLMs) for Verification, Testing, and Design,” IEEE European Test Symposium (ETS), 2025.

Education

Experiences

Client Computing Group

Internship, Beijing, 09/2021 – 12/2021

IC Validator Department

Internship, Shanghai, 05/2020 – 08/2020

Selected Awards

• IEEE Council on Electronic Design Automation (IEEE CEDA) Student Travel Grant, 2024
• IEEE Circuits and Systems (IEEE CAS) Society Student Travel Grant, 2021 and 2025
• First Prize, National Undergraduate Mathematical Contest in Modeling, Tianjin Division, China

Academic Service

Hobbies

Swimming (University PE Score: 100), piano, and painting.